FAQ
Frequently Asked Questions
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Back-end Services
Are there any UMS recommendation for chip soldering?
Please refer to Application Note AN0001 on the UMS website for recommended soldering profiles and guidelines for UMS devices.
How does the UMS QFN service work?
UMS offers a qualified QFN plastic packaging service for both GaN and GaAs technologies. The service includes a leadframe library from UMS secured stock and a checklist for package design rules compliance that must be completed by the customer. A minimum quantity applies for assembly. A dummy wafer option is available for development masks with few pieces, enabling process setup and qualification. For the full QFN design process and leadframe specifications, please contact the foundry support team.
What does BEBO, BEMO, MENT, NTBO, NTMO and NTNT mean?
The delivered dies are classified according to a 4-digit code, coming from French acronyms:
- First 2 digits refer to the electrical sorting: BE = good electrical, ME = bad electrical, NT = not sorted
- Last 2 digits refer to optical sorting: BO = good optical, MO = bad optical, NT = not sorted
Examples: BEBO = good electrical / good optical chips, BEMO = good electrical / bad optical chips, NTNT = not sorted electrically / not sorted optically.
What is the maximum DC current per probe?
The maximum DC current per probe is 500 mA.
How long can wafers be stored on film?
Tape is not set for storage but for shipment. Best practice is likely 6 months duration on tape. For long-term storage, UMS recommends storing wafers in a controlled environment in their original packaging. Please contact foundry support for specific storage recommendations.
How to remove UV tape?
Please contact Foundry Support to get the specific documentation for UV tape removal procedure. UMS provides detailed process notes to customers with back-end service orders.
CAD / Foundry Services
How to install ADS PDKs?
An installation guide is available in the Design Kit.
How to renew ADS PDK licence when expired?
The annual ADS keys can be directly downloaded from your account on the UMS website.
Why do I need a DK agreement to get the PDK?
The DK (Design Kit) / DM (Design Method) IP User Agreement is required to protect UMS intellectual property. The PDK contains proprietary model parameters, layout cells, and process design rules developed by UMS. Signing the agreement ensures that you will use the PDK only for your own design work and will not share or reverse-engineer the content.
Why the DK agreement is only signed by the customer?
This document is an unidirectional agreement. In this phase, only UMS is sharing information on the technologies and these information should not be transferred to third parties or published. The results generated by the customers (including models, design, measurements, circuit topologies) are instead customer IP and are their exclusive property. UMS is committed to protect their confidentiality.
Do I need an export licence in the frame of a Foundry run?
An individual export licence is only required for countries other than the EU, Australia, Canada, Japan, New Zealand, Norway, Switzerland, the UK and the USA. Customers fill in an End-of-Use Certificate (EUC) on request. Validation takes approximately 1 month.
Can we send the PDK to a different unit of our Company?
The PDK is licensed to a specific legal entity (company). If another unit of your company needs access to the PDK, they must sign a separate DK agreement. Please contact UMS foundry support to arrange PDK access for additional company units or subsidiaries.
How can I request a Design Kit (PDK)?
Design Kit access requires a signed DK/DM IP User Agreement. Please visit our Design Kits page to download the agreement and submit your request. You may also register on the UMS Portal to request PDK access online.
How do I participate in a Shared Foundry Run (MPW)?
Visit our Shared Foundry Runs page for the current year's schedule and per-technology offers. Then submit an inquiry through our Foundry Inquiry form and TMT will coordinate your MPW participation with UMS.
Layout
Can I modify the transistor or the diode layout?
The layout of the active devices cannot be modified. In case the customer wants to test a layout modification for development purposes, UMS can accept a derogation after checking the manufacturability of the proposed layout. Nevertheless, UMS cannot commit on neither the model accuracy, nor the device reliability (robustness and life-time) nor the manufacturability yield.
How can I draw a text on my circuit?
Use the alphabet available in the ADS library (Miscellaneous palette) or the gds file provided with Cadence AWR MWO PDK.
In which cases shall I use the pads of the PDK?
The use of the Pad cells provided into the PDK is mandatory in case of On-Wafer test or assembly in UMS, because these pads have the minimum sizes required for UMS services. Customers can use other pads dimensions and pitches if compatible with their measurements and/or assembly processes performed outside UMS.
What are the layout constraints for OWT in UMS?
RF and DC pads from the PDK library are mandatory. One grounded pad per DC pad is recommended. Maximum 15 pads per side. The maximum DC current per probe is 500 mA.
Model
Can I use the model in a region outside the validity domain?
The model can provide simulations outside the validity domain, based on extrapolation. Nevertheless, UMS will not commit on the model accuracy. Please, contact Foundry support for a dedicated analysis.
What are the differences between a linear hot-FET model and a nonlinear hot-FET model?
The linear hot-FET model is for linear simulations only (S parameters, Noise Figure). The nonlinear hot-FET (NLHF) model is for all nonlinear simulations; DC sources are required. Most NLHF models do not include a noise model — use the linear model for noise simulations.
Difference between hot-FET and cold-FET?
The Cold-FET model has the drain biased at 0V (used as a switch). The Hot-FET model requires a drain voltage (used as an amplifier).
How to use the option "via=yes/no" for degenerated transistors source vias?
With via=yes, sources are directly grounded (2-port). With via=no (3-port), sources are accessible. Refer to the Electrical Models chapter of the Design Manual.
Why does GH15 come with different technology versions?
The GH15-1X family allows the customer to choose among several versions for compact design, humidity protection or high-frequency optimized layout.
How to take into account BCB impact on circuit performances?
BCB is taken into account in PDKs in both electrical models and EM stack. Refer to the Design Manual for instructions to enable this option.
MPW (Shared Foundry Runs)
Should I consider dicing street into the MMIC size for the MPW?
Indeed, you have to add 100 µm for GaN technologies or 70 µm for GaAs technologies to the dimension of the die frame.
What is included in a Shared Foundry run (MPW)?
An MPW run is limited to manufacturing and shipment of 20 bare dies per circuit from a PCM good wafer, WITHOUT measurement or optical inspection.
Reliability
Is it possible to go beyond the maximum ratings?
UMS defines two kinds of maximum ratings: ROR (Recommended Operating Ratings) and AMR (Absolute Maximum Ratings). ROR should be respected for long life-time; going beyond ROR is possible for an undefined time but UMS won't guarantee reliability or model accuracy. Beyond AMR can lead to catastrophic failures.
Space Applications
What are the Space derating rules to be applied during the circuit design phase?
General space derating rules are the following: 75% of AMR if < ROR or ROR values. Please check latest ESA standards at: https://escies.org/webdocument/showArticle?id=167&groupid=6.
What is the flow for wafer space qualification?
The qualification flow includes: WAT based on DC and RF tests, space visual inspection Cond. A, wire bond and die shear tests, and SEM.
What is the useful surface on a 4-inch wafer?
About 6,080 mm² (GaAs and GaN).
Tile Building
Do I have to build the tile by myself?
UMS will take care of tile building to optimize space and maximize circuits per wafer. Customers can provide a tile drawing for specific requests. Leave free area for PCM.
What are the dimensions of the dicing streets?
The path must be free of metallisation. The dicing street width is 100 µm for GaN and 70 µm for GaAs, added by UMS during tile building.
How to use the die frame for circuit layout?
The circuit layout is delimited by the die frame. The final MMIC dimension equals the die frame plus the dicing streets.
How to place e-beam marks?
At the 4 corners of each circuit, with the same orientation for all (horizontal or vertical).
Can I choose different orientation for transistor gates?
No. All gates must have the same orientation (horizontal).
What is the tolerance after dicing?
The tolerance after dicing is half the dicing street: ±50 µm for GaN and ±35 µm for GaAs.
What are the minimum chip dimensions?
Recommended minimum chip dimensions are 800 µm × 800 µm.
Glossary of Terms
The following acronyms and terms are commonly used in UMS foundry services and technical documentation.
Still Have Questions?
Contact our foundry experts for personalized technical support and guidance on UMS foundry services. For urgent foundry inquiries, you may also reach the UMS Foundry Team directly.
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