GaAs pHEMT Foundry Process
0.15 μm and 0.25 μm gate length options - DC to 105 GHz, space-qualified
UMS GaAs pHEMT Process
In-house developed, space-qualified GaAs pseudomorphic HEMT technology for custom MMICs
UMS offers two GaAs pHEMT process options: 0.15 μm gate length for ultra-low-noise and high-frequency applications up to 105 GHz, and 0.25 μm gate length for general-purpose RF and microwave designs up to 50 GHz. Both processes are fully characterized with PDK support, and are listed on the ESA EPPL (European Preferred Parts List) for space applications.
Process Options
Two gate length options to match your performance and cost targets
0.15 μm pHEMT
Frequency: DC to 105 GHz
Application: LNAs, mixers, wideband receivers
Noise Figure: Typical 0.5 dB @ 10 GHz
VDS: 5 V typical
0.25 μm pHEMT
Frequency: DC to 50 GHz
Application: General-purpose RF, drivers, gain blocks
Noise Figure: Typical 0.8 dB @ 10 GHz
VDS: 5 V typical
Dual-Gate Options
0.15 μm dual-gate: For Switching and variable-gain applications
Integrated passives: Thin-film resistors, MIM capacitors, spiral inductors
Backside via: Low-inductance ground connection
Process Features
Complete process stack for high-performance MMIC design
Active Devices
pHEMT transistors with ft up to 120 GHz (0.15 μm). Optional HBT (Heterojunction Bipolar Transistor) for higher linearity and current drive capability.
Passive Elements
Thin-film NiCr resistors (50 Ω/sq), MIM capacitors (400 pF/mm²), spiral inductors (air-bridge crossover), and CPW/microstrip transmission lines.
Metalization
Ti/Pt/Au Schottky gate metalization. Optional Au air-bridge for low-parasitic interconnect. 2-4 metal layers depending on process option.
Via & Backside
Through-substrate via holes (laser or etching) for low-inductance ground. Wafer thinning to 100 μm or 50 μm optional for improved thermal and high-frequency performance.
Design Support
Full PDK and design rule support for fast time-to-market
Process Design Kit (PDK)
Complete PDK available for Keysight ADS, Cadence AWR, and ANSYS HFSS. Includes device models, layout cells, design rule checking (DRC), and layout vs. schematic (LVS) decks.
Design Rule Manual
Comprehensive design rule documentation covering layout geometry rules, layer stacking, metal spacing, via placement, and RF grounding guidelines.
Foundry Design Review
UMS engineering team provides design rule checking and design review services before tape-out, reducing design iteration risk and ensuring first-pass success.
Ready to design with GaAs pHEMT?
Contact TMT to request PDK access, process design manuals, and design review support for your custom MMIC project.
Foundry Inquiry